我收到以下错误：
java.lang.IllegalArgumentException: requirement failed: must be inside Builder context当我在终端上写这个时出现问题：sbt run
这是我的代码：
import chisel3._
class combinedTausworthe extends Module {
val io = IO(new Bundle {})
val seed1 = RegInit(322769304.U(32.W))
val seed2 = RegInit(424235419.U(32.W))
val seed3 = RegInit(212119443.U(32.W))
var result = 0.U
var b = ((seed1 << 13)(31, 0) ^ seed1)
seed1 := ((seed1 & 4294967294L.U) << 12)(31, 0) ^ b
b := ((seed2 << 2)(31, 0) ^ seed2) >> 25
seed2 := ((seed2 & 4294967294L.U) << 4)(31, 0) ^ b
b := ((seed3 << 3)(31, 0) ^ seed3) >> 11
seed3 := ((seed3 & 4294967294L.U) << 17)(31, 0) ^ b
result := (seed1 ^ seed2 ^ seed3)
println(result)
}
object Main extends App {
val variable = Module(new combinedTausworthe())
}回答1
对于设计顶部的实例化，您需要调用 ChiselStage 或其他一些入口点函数。
如果您想编译和转储 Verilog，请尝试：
object Main extends App {
emitVerilog(new combinedTausworthe) // this was added in v3.5.0
// If you are using a version older than v3.5.0, use the following
(new chisel3.stage.ChiselStage).emitVerilog(new combinedTausworthe)
}如果您只想获得可以打印的 String，请尝试以下操作：
object Main extends App {
println(getVerilogString(new combinedTausworthe)) // this was added in v3.5.0
// If you are using a version older than v3.5.0, use the following
println(chisel3.stage.ChiselStage.emitVerilog(new combinedTausworthe))
}